AMD “Zen 6” Support Verified on AM5 Motherboards with 32 MB and 64 MB BIOS Chips

With the first “Olympic Ridge” designs scheduled to debut on the well-known AM5 socket, AMD is preparing to unveil the “Zen 6” family of CPUs. It is anticipated that Zen 6 will continue to uphold the company’s pledge to preserve socket compatibility throughout several generations. Yet, larger BIOS ROM chips—which have grown from the typical 32 MB to 64 MB—are becoming more and more common on contemporary motherboards. All of the required microcode for different processor versions must be supported because the AM5 platform is designed to handle many CPU generations. Due to space limitations, several manufacturers have already stopped supporting older CPUs in their more recent BIOS versions.

Companies frequently utilize marketing terms like “Future CPU Ready” or “Ultimate Compatibility,” but they haven’t been very explicit about the reasons behind this transition. AMD has not formally confirmed Zen 6 compatibility with AM5, thus it’s interesting that ASUS noted “Zen 6” support in marketing papers for the X870 AYW GAMING WIFI W. HXL, a well-known hardware leaker, verified over the weekend that Zen 6 will run on both 600 and 800-series boards, regardless of whether they had 32 MB or 64 MB BIOS chips. The news is comforting. One unanswered concern, though, is whether manufacturers will begin to remove Zen 4 support from those 32 MB boards in order to create place, much like what happened with the first-generation Zen when Zen 3 was introduced on 16 MB boards. For anyone buying motherboards now and intending to upgrade when Zen 6 CPUs become available, this is probably a major worry.

Like all AMD Ryzen desktop CPUs since the Ryzen 3000 series, the Olympic Ridge generation will feature a chiplet-based processor. It is expected that these processors will have Zen 6 cores in CPU complex dies (CCDs) made with TSMC’s 2 nm N2 technology. AMD is anticipated to raise the number of CPU cores per CCD for the first time in these generations. A novel client I/O die (cIOD), most likely based on TSMC’s 4 nm N4P node, is also anticipated to be introduced by the chip. With an improved set of DDR5 memory controllers that support faster speeds, this new cIOD is anticipated to have a substantially lower TDP than the existing 6 nm version.