AMD “Zen 6” SKUs with 3D V-Cache May Have Up to 288 MB of Cache
AMD’s anticipated “Zen 6” client processors are likely to maintain the trend of providing optional SKUs featuring 3D V-Cache, akin to those before them. Nonetheless, these upcoming processors could have considerably greater cache sizes than the existing “Zen 5” models in the “Granite Ridge” lineup. As reported by HXL on X, the single-CCD variant will feature 144 MB of 3D V-Cache, whereas the dual-CCD setup will come with 288 MB of cache. This indicates that AMD will retain its well-known CPU architecture featuring a client I/O die and two distinct CCDs, both of which will gain from enhanced cache capacity.
This method closely resembles Intel’s forthcoming “Nova Lake” processors, which are also expected to gain a significant increase in cache size via the large Last Level Cache (bLLC). Speculations indicate that these will provide 144 MB for SKUs featuring a single compute die and 288 MB for models with two compute dies. Intel utilizes bLLC in its “Clearwater Forest” server processors as a passive interposer, embedding local cache underneath active tiles. Incorporating this technology into conventional gaming chips could greatly improve performance, making them formidable rivals to the forthcoming “Zen 6” processor series.
For “Zen 6,” AMD intends to position the CPU CCD on TSMC’s N2P 2 nm variant and develop the cIOD on the N3P 3 nm node. Moreover, the enhanced cache size will be supported by sophisticated x86-64 instruction extensions such as AVX512_BMM, AVX512_FP16, AVX_NE_CONVERT, AVX_IFMA, and AVX_VNNI_INT8, among others. This is especially significant since 16-bit AVX-512 computations will now be achievable on consumer desktop CPUs, offering an additional performance enhancement with a nearby rapid memory pool.
