Intel “Nova Lake” May Receive a 144 MB Cache Boost from bLLC
One of the most trusted Intel leakers reports that the forthcoming Intel “Nova Lake” desktop CPUs will feature 144 MB of bLLC cache to enhance their current cache setup, providing Intel with a counterpart to AMD’s 3D V-Cache for improved gaming. Intel currently utilizes bLLC in its “Clearwater Forest” server processors as a passive interposer, integrating local cache below active tiles, so its addition to a standard gaming chip could provide a notable performance boost. According to the latest leak, the bLLC implementation will occur on the compute tile, placing it near the substantial core cluster Intel is set to launch.
The leading 52-core SKU features a tiled architecture that combines two compute tiles alongside one SoC tile. Every compute tile contains eight P-Cores derived from “Coyote Cove” and 16 efficient E-Cores from “Arctic Wolf,” and the SoC tile provides four low-power Arctic Wolf LPE-cores. This results in a configuration of 16 P-Cores, 32 E-Cores, and 4 LPE-Cores for Nova Lake-S, summing up to 52 cores for the highest SKU, while single-tile versions provide a 28-core alternative. Given the presence of two compute tiles, we need to consider whether Intel will utilize one 144 MB bLLC block for the full dual-tile group or if it will feature two separate 72 MB blocks.
The desktop platform “Nova Lake-S” is anticipated to be called the Intel Core Ultra 400 Series and will include various next-gen IP. This encompasses the NPU 6, which is said to achieve as much as 74 INT8 TOPS. Moreover, major platform modifications feature the backing and reinstatement of the AVX-512 subset along with its AVX10.2 superset. This announcement resolves months of speculation indicating that Nova Lake would not be compatible with AVX10.2 and other advanced x86 technologies such as APX/AMX. Lastly, Xe3P GPU IP will be used by Intel in different versions.
