Pictured is an AMD Navi 31 RDNA3 GPU.

Here is the first image of AMD’s fastest next-generation graphics cards’ “Navi 31” GPU. This will be AMD’s ambitious attempt to create the first multi-chip module (MCM) client GPU with more than one logic die, based on the RDNA3 graphics architecture. With Intel’s “Ponte Vecchio,” MCM GPUs are not new in the enterprise market, but this would be the first MCM GPU designed for high-end gaming graphics devices. AMD has previously produced MCM GPUs, but those were packaged with a single logic die encircled by memory stacks. “Navi 31” is an MCM with up to eight logic dies but no memory stacks (the graphic below does not show HBM stacks).

According to rumors, “Navi 31” contains one or two SIMD chiplets known as GCDs that house the RDNA3 compute units, the GPU’s primary number-crunching apparatus. The most cutting-edge silicon fabrication node, perhaps TSMC’s 5 nm EUV, was probably used to make these chiplets, but we won’t know for sure. The chip’s 384-bit wide GDDR6 memory controllers will be housed on separate chiplets that are constructed using a somewhat older node, such as TSMC 6 nm. This is not multi-GPU-a-stick since, in addition to the various ancillaries, both SIMD chiplets have uniform access to the whole 384-bit wide memory bus (which is not 2x 192-bit but 1x 384-bit). The 20 Gbps GDDR6 memory chips required by JEDEC are anticipated to be placed all around the “Navi 31” MCM.