The 5th Gen EPYC “Turin,” AMD’s upcoming server processor, has been pictured as an engineering sample that is likely being assessed by the company’s cloud or data center clients. The processor’s high-density cloud-focused variant, which uses “Zen 5c” CPU cores, boasts an astounding 192 cores and 384 threads. A relatively high core count of 128 cores and 256 threads is included in its regular version, which employs larger “Zen 5” cores that can sustain higher clock speeds. This is in contrast to the 96 cores and 192 threads of the “Zen 4” based EPYC “Genoa.”

With up to 16 CCDs (CPU complex dies) surrounding the updated sIOD (server I/O die), the EPYC “Turin” server processor based on “Zen 5” The TSMC N4P foundry node, which is a more developed variant of the TSMC N4 node AMD currently uses for its “Phoenix” client processors, and the TSMC N5 node it uses for its “Zen 4” CCD are anticipated to be the sites of AMD’s CCD assembly. According to TSMC, the N4P node provides a 6% increase in transistor density and a power efficiency gain of up to 22% over the N5 node. It has been verified that each of the “Zen 5” CCDs has eight CPU cores sharing 32 MB of L3 cache memory.The processor’s 128 cores and 256 threads are the result of 16 of these CCDs combined. A totally different animal is the high-density “Turin” designed for cloud data centers.

Twelve “Zen 5c” CCDs are used by the “Turin” CPU. The “Zen 5c” is a physically compressed version of the bigger “Zen 5” core, similar to what “Zen 4c” is to “Zen 4,” with the same ISA (instruction sets) and IPC, however it usually operates at slower clock speeds than the standard “Zen 5” cores. It is designed for CPUs with a lot of cores. Similar in sIOD to the standard “Turin,” the high-density “Turin” MCM features 12 “Zen 5c” CCDs instead of 1. 16 “Zen 5c” cores on each CCD share a 32 MB L3 cache. This is interesting—as you may remember, the Zen 4c CCD that is now in use has two CPU core complexes (CCXs) with eight “Zen 4c” cores per that share a 16 MB L3 cache.The overall accessible L3 cache is doubled by the “Zen 5c” CCD.