The GeForce RTX 40-series is poised to revolutionize the way NVIDIA generally avoids reducing the PCIe lane counts on its mid-range GPUs, doing so only with its most entry-level SKUs. According to a VideoCardz report, the next GeForce RTX 4060 Ti, which is built on the AD106 chip, has a PCI-Express 4.0 x8 host interface.

Using the RTX 4060 Ti on older platforms, such as the 10th Gen Intel Core “Comet Lake,” or even much newer processors, such as the AMD Ryzen 5700G “Cezanne,” would run the GPU at PCI-Express 3.0 x8, as the GPU physically lacks the remaining 8 lanes. However, this is still plenty of interface bandwidth for a GPU of this market segment, with bandwidth comparable to that of PCI-Express 3.0 x16. For AIC partners, the decreased PCIe lane count should make board design simpler because less PCB traces and SMDs are required for each every PCIe lane. PCIe traces are painstakingly constructed by EDA software (and then confirmed) to be the same length across all lanes for signal integrity, much like DRAM chip traces are.