More Advanced 3 nm Node Used To Produce AMD “Zen 5c” CCDs Than “Zen 5”
According to a rumor by Chinese website UDN, AMD is allegedly constructing its future “Zen 5” and “Zen 5c” CPU Core Dies (CCDs) on two separate foundry nodes. The 4 nm EUV foundry node, which is a little more advanced than the current 5 nm EUV the firm is constructing “Zen 4” CCDs on, is apparently where the Zen 5 CCD, which will power the next Ryzen “Granite Ridge” desktop CPUs, “Fire Range” mobile processors, and EPYC “Turin” server processors, will be manufactured. On the other side, the report states that the “Zen 5c” CCD, or the chiplet with only “Zen 5c” cores in a high density layout, will be constructed on an even more sophisticated 3 nm EUV foundry node. The second half of 2024 will see the mass production of both CCDs, with commercial releases anticipated.
The enormous 32 cores of the “Zen 5c” chiplet are divided between two CCXs, each with 16 cores. A 32 MB L3 cache is shared by 16 cores on each CCX. AMD may be using the 3 nm foundry node to pack these 32 cores—each with 1 MB of L2 cache—and a total of 64 MB of L3 cache. Voltages could be an additional factor. The “Zen 5c” core, without any alteration in IPC or instruction sets, is a highly condensed version of “Zen 5,” operating at a lower voltage band than its larger brother, if “Zen 4c” is any indication. The choice of 3 nm may have been made with the intention of raising clock speeds at those lower voltages in an effort to use clock speeds—rather than IPC and core count—to increase performance generationally. There will be no more than six of these big CCDs in the EPYC processor with “Zen 5c” chiplets, for a maximum core count of 192. Only 8 cores in a single CCX make up the standard “Zen 5” CCD. The cores share 32 MB of L3 cache, and TSV provision for 3D Vertical Cache allows the L3 cache to be increased in special variations.
