Both the AMD Ryzen 9 9950X3D and 9900X3D CCD chips will have a 3D V-cache.
Rumors surfaced earlier this week suggesting AMD is pushing hard to deliver the Ryzen 7 9800X3D 8-core/16-thread “Zen 5” processor with 3D V-cache by late October. The well-liked 7800X3D is replaced by the 9800X3D, and AMD presumably wants to have a competitive gaming processor ready for the arrival of Intel’s Core Ultra 2-series “Arrow Lake-S” in time. Because of rumors that the chips include certain “new features” over their predecessors, the 7950X3D and 7900X3D, the higher core-count 9000X3D series CPU models, the Ryzen 9 9950X3D and Ryzen 9 9900X3D, were expected to launch sometime in Q1 2025.We also looked into the potential of AMD providing 3D V-cache to both of the processor’s 8-core CCDs at the time. As it happens, things are going in this direction.
The higher core count 9950X3D and 9900X3D are reportedly going to integrate 3D V-cache on both CCD chiplets, according to a recent report from Benchlife.info. This will give these processors an astonishing 192 MB of L3 cache (96 MB each CCD) and 208 MB or 204 MB of “total cache” (L2+L3). According to the rumor, AMD is also preparing a Ryzen 5 9600X3D chip, which would be its second attempt to compete with Intel’s Core i5 series. AMD released the Ryzen 5 7600X3D relatively recently, however it fell 1-3% shy of the Core i5-14600K in gaming workloads. Whether the 9600X3D will go on sale in October with the 9800X3D or in Q1-2025 with the Ryzen 9 9000X3D series is unknown.
Although it is unclear from the reference to SOC configuration if this is from 3DVCache, placed on top of the CCD, or something else, the documentation states that the maximum L3 cache is 96 MB.
The inclusion of 3D V-cache on the 9950X3D and 9900X3D CCDs could be intriguing, given that both chiplets can handle gaming workloads at a consistent level of performance. Multithreaded productivity workloads are permitted to distribute across both CCDs on the 7950X3D and 7900X3D, but gaming workloads are scheduled to the CCD with the 3D V-cache thanks to OS scheduler-level QoS logic.
