AMD is gradually planning to dispatch its cutting edge customer situated sped up handling unit (APU), which is AMD’s method of signifying a CPU+GPU mix. The future plan is codenamed after Van Gogh, showing AMD’s constant utilization of noteworthy names for their items. The APU is accepted to be a plan like the one found in the SoC of the most recent PlayStation 5 and Xbox Series X/S supports. That implies that there are Zen 2 centers present alongside the most recent RDNA 2 designs, next to each other in a similar processor. Today, one of AMD’s architects posted a boot log of the quad-center Van Gogh APU designing example, showing some fascinating data.

The boot log contains data about the memory type utilized in the APU. In the logs, we see a section that says “[drm] RAM width 256bits DDR5”, which implies that the APU has an interface for the DDR5 memory and it is 256-digit wide, which addresses a quad-channel memory design. A wide memory transport is commonly utilized for applications that need loads of data transfer capacity. Given that Van Gogh utilizes RDNA 2 illustrations, the organization needs an adequate memory transmission capacity to hold the GPU back from starving for information. While we don’t have considerably more data about it, we can hope to hear more noteworthy subtleties soon.