The next-generation “Zen 4” CPU microarchitecture powering AMD’s 4th Gen EPYC “Genoa” enterprise processors, will support 512-bit AVX instruction sets, according to an alleged company slide leaked to the web on the ChipHell forums. The slide references “AVX3-512” support in addition to BFloat16 and “other ISA extensions.” This would make “Zen 4” the first AMD microarchitecture to support AVX-512. It remains to be seen which specific instructions the architecture supports, and whether all of them are available to both the enterprise and client implementations of “Zen 4,” or whether AMD would take an approach similar to Intel, in only enabling certain “relevant” instructions on the client parts. The slide also mentions core counts being “greater than 64” corresponding with our story from earlier today.

Sources: ChipHell Forums, via VideoCardz , Techpowerup