A Combination of TSMC N2 and N3 Nodes Will Be Used by AMD “Zen 6” Processor Families
According to PowerPoint decks distributed to engineers at three major motherboard vendors, AMD’s next Zen 6 CPU family will make use of TSMC’s N3 and N2 manufacturing nodes. These documents list five different silicon lines for servers, desktops, and notebooks that will be available in late 2026. Regarding servers, the EPYC “Venice” lineup is divided into two categories: Venice dense for high-density cloud racks and Venice classic for general-purpose deployments. Both versions offer an 8–10% clock-speed increase over the current N3E by utilizing TSMC’s specially tuned N2P technology. When eight dies are joined using the current organic interposer, 256-core, 512-threaded dense packages are possible. At the same time, each classic die expands to 12 Zen 6 cores, and each dense die contains 32 Zen 6c cores.
AMD has chosen codenames for its client systems that allude to the types of users they are meant to serve. “Gator Range” is aimed at gaming laptops that weigh more than 55 W, while “Olympic Ridge” will power the Ryzen 10000 desktop series on the N2P node. With entry-level models choosing a cost-effective monolithic N3P die, “Medusa Point,” which has a hybrid design that combines a N2P compute tile with a N3P I/O tile, will cater to the mainstream thin-and-light market. The roadmap also includes a more in-depth “Medusa Halo” and the cost-conscious “Bumblebee” series, albeit their process assignments are still being reviewed. The finished silicon closely resembles a “N2‑AMD” stack rather than a typical N2P node since AMD and TSMC closely co-optimize metal layers and libraries. Volume ramps are scheduled for the back-to-school 2026 notebook cycle and a later server refresh wave, with the first silicon likely to return from the fabrication facility before Christmas.
