JEDEC Publishes DDR4 NVDIMM-P Bus Protocol Standard

JEDEC Solid State Technology Association, the global leader in standards development for the microelectronics industry, today announced the publication of JESD304-4.01 DDR4 NVDIMM-P Bus Protocol. The JEDEC NVDIMM-P standard will enable the industry to create advanced memory solutions that benefit from the enhanced system performance and novel data availability offered by Persistent Memory devices. JESD304-4.01 DDR4 NVDIMM-P is available for download from the JEDEC website.

As demand for DRAM capacity and bandwidth continues to grow, Hybrid DIMM technologies such as NVDIMM-P provide an innovative method for attaching emerging Persistent Memory in computing systems. Combining the access speeds of DDR with the reliability and capacity of non-volatile memories gives design engineers a new approach to data management. Much more than a standard DIMM specification, NVDIMM-P provides a full transactional interface protocol compatible with standard DRAM DIMMs along with a firmware programming model for the modules. NVDIMM-P simultaneously maximizes both re-use and flexibility by minimizing system host changes, providing an interface of the lowest latency to emerging memory, and offering flexible support for varied Persistent Memory media characteristics and use cases.

NVDIMM-P enables:

• Persistence: lowest latency and high bandwidth access to Persistent Memory modules in a system
• Abstraction of Memory Media: enabling most any memory media on the DDR channel
• Higher Memory Capacity: supports expanded memory addressing
• Plug and Play Interoperability: physically plugs into standard dual in-line memory module (DIMM) sockets and run-time interoperable with DDR DRAM DIMMs on the same bus

Key features include:

• Fully compatible with existing DDR channels (Physicals, Electricals, Protocol, Clocking)
• Minimal to no pin adder in CPU socket
• Protocol support of non-deterministic latency for data reads
• Transactional operations for ensuring data is preserved in Persistent Memory
• Latency support from NAND Flash down to DRAM latency (at module level)
• Self-contained reliability + link error protection

Mian Quddus, Chairman of the JEDEC Board of Directors, said: “Increasing performance requirements are driving the need for more advanced technologies, and the standardization of the new generation Persistent Memory modules such as NVDIMM-P will be essential to fulfilling those needs.” He added, “We invite all interested engineers worldwide to visit the JEDEC website for more information about JEDEC membership and participation in JEDEC standards-setting activities.”

Source: TechpowerUP