Annotated AMD “Strix Point” Die Displays Zen 5 + Zen 5c Core Layout

AMD unveiled its Ryzen AI 300 series of mobile processors on Monday, built around the 4 nm “Strix Point” monolithic silicon technology. AMD stated that the maximum CPU core configuration for this chip was 12-core/24-thread, which would represent a tidy 50% increase in core counts over the previous generation. However, there is more to this chip than meets the eye. Even though “Strix Point” incorporates “Zen 5,” not every one of the silicon’s 12 CPU cores is the standard version of “Zen 5.” Physically, the device has eight “Zen 5c” compact cores and four “Zen 5” cores. Nemez (GPUsAreMagic) made an effort to annotate the “Strix Point” die using a high-resolution image taken during AMD’s Computex keynote by System360Cheese. Some intriguing results were found.

The annotation shows that a 16 MB L3 cache is shared by the four conventional “Zen 5” cores, each of which has a dedicated 1 MB L2 cache. In contrast, it appears that the eight “Zen 5c” cores—possibly housed in a different CCX—share a smaller 8 MB L3 cache. Also, each of them has a 1 MB L2 cache. When assessed using typical INT and FP benchmarks that don’t transport a lot of data, the “Zen 5c” cores have the same IPC as the “Zen 5” cores; nevertheless, it may lag behind in workloads with a lot of streaming data. Furthermore, because the physically compacted cores were unable to maintain higher core voltages, the prior generation “Zen 4c” cores were typically restricted to lower frequencies than conventional “Zen 4” cores. Should that be the case with “Zen 5c,” then “Strix Point” is actually a fascinating hybrid core configuration including eight cores with high-IPC efficiency.